Hardware implementations of artificial neural networks (ANNs)—the most advanced of which are made of millions of electronic neurons interconnected by hundreds of millions of electronic synapses—have achieved higher energy efficiency than classical computers in some small-scale data-intensive computing tasks. State-of-the-art neuromorphic computers, such as Intel’s Loihi or IBM’s NorthPole, implement ANNs using bio-inspired neuron- and synapse-mimicking circuits made of complementary metal–oxide–semiconductor (CMOS) transistors, at least 18 per neuron and six per synapse. Simplifying the structure and size of these two building blocks would enable the construction of more sophisticated, larger and more energy-efficient ANNs.
In this talk, Prof. Mario Lanza, IEEE Fellow and IEEE Electron Devices Society Distinguished Lecturer, will explain how a single CMOS transistor can exhibit neural and synaptic behaviors if it is biased in a specific (unconventional) manner. By connecting one additional CMOS transistor in series, we build a versatile 2-transistor-cell that exhibits adjustable neuro-synaptic response (which we named neuro-synaptic random access memory cell, or NS-RAM cell). This electronic performance comes with a yield of 100% and an ultra-low device-to-device variability, owing to the maturity of the silicon CMOS platform used—no materials or devices alien to the CMOS process are required. These results represent a short-term solution for the implementation of efficient ANNs and an opportunity in terms of CMOS circuit design and optimization for artificial intelligence applications. The MOSFET transistor keep surprising us and now—after this study—it seems to be the perfect building block for implementing ANNs.
Speaker(s): Dr. Mario Lanza
Virtual: https://events.vtools.ieee.org/m/484279